In recent years, large-scale multi-processor systems have been put into practice, and simultaneously a software technique using a plurality of processors has progressed. This multi-processor system is composed of a plurality of processors and a shared memory, and is constituted so that the plural processor are operated in parallel, thereby improving processing speed, throughput and reliability so as to compose a computer system having higher performance than that of a single processor. In the multi-processor system, it is indispensable to keep coherence of data between the processors, and this coherence is maintained by using a queue on the shared memory according to various methods.
FIG. 14 is a block diagram showing a structure of a conventional multi-processor system. For explanation, in the multi-processor system shown in this diagram, a writing processor 1 and a reading processor 2 are provided to a writing side and a reading side respectively. The writing processor 1 and the reading processor 2 are connected accessibly to a shared memory 3 via a data bus B. This shared memory 3 is a memory as a resource which is commonly used between the writing processor 1 and the reading processor 2. Three or more processors are occasionally provided according to a scale of systems.
The writing processor 1 has an arithmetic section 1a for performing various arithmetic calculations, a data reading section 1b for reading data from the shared memory 3 via the data bus B, and a data writing section 1c for writing data into the shared memory 3 via the data bus B. Similarly, the reading processor 2 has an arithmetic section 2a, a data reading section 2b and a data writing section 2c. 
There will be explained below an example that data communication is performed from the writing processor 1 to the reading processor 2 via the data bus B and the shared memory 3. This communication is performed via a queue (waiting line) 4 on the shared memory 3 as shown in FIG. 15 in order to maintain coherence of data between the processors. Namely, the communication data are written into the shared memory 3 by the writing processor 1 and are read by the reading processor 2 so as to be transmitted from the writing processor 1 to the reading processor 2.
The writing processor 1 performs the following operations:                A1. Securing a memory area for communication;        A2. writing communication data (information) into the memory area; and,        A3. registering the secured memory area into the queue 4.        
More concretely, in the operation A1, the memory area into which communication data (information) to be transmitted to the reading processor 2 are written is secured in the shared memory 3. In the operation A2, the communication data are written into the memory area secured in the operation A1. Further, in the operation A3, the memory area secured in the operation A1 is registered in the queue 4. Here, the memory area and the queue 4 exist on the shared memory 3, and they are referred to by a plurality of processors. As a result, it is necessary to protect them by means of exclusive lock, mentioned later.
Further, the above-mentioned operation A3 has concretely the following steps:                A3-1. obtaining exclusive lock which protects the queue 4,        A3-2. operating the queue 4, and        A3-3. releasing the exclusive lock which protects the queue 4.        
The reading processor 2 performs the following operations:                B1. obtaining a memory area form the queue 4,        B2. reading communication data (information) from the memory area, and        B3. releasing the memory area when the communication (reading) is ended.        
More concretely, in the operation B1, a memory area into which communication data are written is obtained by the reading processor 2 in the shared memory 3. In the operation B2, the communication information is read from the memory area obtained in the operation B1. Further, in the operation B3, the memory area obtained in the operation B1 is released.
The operation B1 has the following steps:                B1-1. obtaining exclusive lock which protects the queue 4,        B1-2. operating the queue 4, and        B1-3. releasing the exclusive lock which protects the queue 4.        
A structure of the queue 4 (see FIG. 15) in the conventional multi-processor system, and the writing/reading operation will be explained here with reference to FIG. 16. The queue 4 shown in top of FIG. 16 has elements 5a, 5b and 5c which are linked together, memory areas 6a, 6b and 6c corresponding to the elements 5a, 5b and 5c respectively, a registering place information area 7, and a obtaining place information area 8. Connection information which shows that a connecting destination is the element 5b is written into the element 5a, and similarly connection information which represents that a connecting destination is the element 5c is written into the element 5b. Namely, the connecting relationship in the elements 5a, 5b and 5c is defined by the connection information.
Communication data are registered (written) into the memory areas 6a, 6b and 6c by the writing processor 1 (see FIG. 15). Further, the respective communication data registered into the memory areas 6a, 6b and 6c are obtained (read) by the reading processor 2 (see FIG. 15). Registering place information relating to registering place of the communication data (elements, memory areas) is written into the registering place information area 7 by the writing processor 1. Moreover, the communication data are written into the memory area which is specified by the registering place information. Obtaining place information relating to an obtaining place (elements, memory areas) of the communication data is written into the obtaining place information area 8 by the reading processor 2.
The diagram in the middle of FIG. 16 explains an operation of the queue 4 at the time of registering by means of the writing processor 1. At the time of the registering, the above-mentioned exclusive lock is put on the queue 4 so that only the writing processor 1 operates the queue 4. This exclusive lock protects the queue 4 from processors other than the writing processor 1 (in this case, the reading processor 2). In this drawing, the writing processor 1 obtains the exclusive lock and secures the memory area 6d (element 5d) after obtaining the exclusive lock. Next, the writing processor 1 writes the communication data into the memory area 6d, and updates the registering place information written into the registering place information area 7.
More concretely, when the registering place information relating to the memory area 6c (element 5c) is written into the registering place information area 7, the writing processor 1 updates the registering place information into registering place information relating to the memory area 6d (element 5d) which is the next registering destination. Here, when communication information is not written into any memory areas, the writing processor 1 performs the operation on the registering place information of the registering place information area 7, and also performs an operation on obtaining place information of the obtaining place information area 8. Further, the writing processor 1 performs the operation on the connection information which defines a connection relationship between the element 5c and the element 5d, and releases the exclusive lock.
The diagram in the bottom of FIG. 16 explains the operation of the queue 4 at the time of obtaining by means of the reading processor 2. At the time of the obtaining, similarly to the writing processor 1, the exclusive lock is put on the queue 4 so that only the reading processor 2 operates the queue 4. In this drawing, the reading processor 2 obtains the exclusive lock, and obtains the memory area 6a (element 5a) based on the obtaining place information of the obtaining place information area 8. Next, the reading processor 2 reads the communication data written into the memory area 6a, and releases this memory area. The reading processor 2 updates the obtaining place information written into the obtaining place information area 8.
More concretely, when obtaining place information relating to the memory area 6a (element 5a) is written into the obtaining place information area 8, the reading processor 2 updates the obtaining place information into obtaining place information relating to the memory area 6b (element 5b) which is the next obtained destination. Here, when communication information is not written into any memory areas, the reading processor 2 performs the operation on the obtaining place information of the obtaining place information area 8, and also performs the operation on the registering place information of the registering place information area 7. Further, the reading processor 2 performs the operation on the connection information in order to release the connection between the element 5a and the element 5b shown in FIG. 16(a), and releases the exclusive lock. In such a manner, the writing processor 1 and the reading processor 2 perform the operations on three pieces of information such as (A) connection information, (B) registering place information and (C) obtaining place information.
In the conventional processor system, for example, the operations (obtaining/releasing) relating to the exclusive lock in A3-1 and A3-3, and the operations (obtaining/releasing) relating to the exclusive lock in B1-1 and B1-3 require longer time than normal memory operations such as reading and writing from/into a memory. For this reason, there arises a problem that a processing speed is lowered.
Practically, the writing processor 1 and the reading processor 2 communicate while protecting data to be treated via the exclusive lock, and access from a plurality of processors is concentrated on the exclusive lock. This causes a deterioration of the software performance. In addition, when the access is not concentrated on the exclusive lock, the operation relating to the exclusive lock require time which is 100 to 1000 times as much as the normal memory access. For this reason, the above problem cannot be ignored when fine data are treated.
In addition, instead of the exclusive lock, there exists a method of protecting a memory exclusively by performing the writing operation and the reading operation inseparably on the queue 4. However, also in this case, since the processing time becomes long similarly to the exclusive lock, this method does not solve the problem basically.